Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Considering that today's semiconductor chips can have billions of components, EDA tools are essential for their design.
Although the languages and tools of EDA tools have evolved significantly over the years, the general approach of specifying the desired behavior in a textual programming language and letting the tools derive the detailed physical design remains the basis of digital IC design today.
While the goal is for a physical design to work properly—meaning all the functionalities are performed as intended—this is not always the case. Designers also employ electronic circuit simulation tools which are essentially mathematical models used to replicate the behavior of an actual electronic device or circuit. In this regard, simulation tools allow for modeling of circuit operation and are an invaluable analysis tool. Simulating a circuit's behavior before actually building it can greatly improve design efficiency by making faulty designs known as such, and providing insight into the behavior of electronics circuit designs. In particular, for integrated circuits, the tooling (photomasks) is expensive, breadboards are impractical, and probing the behavior of internal signals is extremely difficult. Therefore, almost all IC design relies heavily on simulation.
Static timing analysis (STA) is a simulation method of computing the expected timing of a digital circuit without requiring a simulation of the full circuit.
High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Gauging the ability of a circuit to operate at the specified speed requires an ability to measure, during the design process, path delay along relevant routes (critical paths). Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing.
For proper circuit operation in a typical synchronous digital system, data is supposed to move in lockstep, advancing one stage on each cycle of the clock signal. This is enforced by synchronizing elements such as flip-flops or latches, which copy their input to their output when instructed to do so by the clock. Only two kinds of timing errors are possible in such a system. One such error is a setup time violation, which is when a signal arrives too late, and misses the time when it should advance. The other error is a hold time violation, which is when an input signal changes too soon after the clock's active transition.
The time when a signal arrives can vary due to many reasons—the input data may vary, the circuit may perform different operations, the temperature and voltage may change, and there are manufacturing differences in the exact construction of each part. The main goal of static timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured.
Because static time analysis is capable of verifying every path, it can detect other problems like glitches, slow paths and clock skew.
A “critical” path is defined as the path between an input and an output with the maximum delay. Once the circuit timing is determined for a set of paths of varying propagation delay, the critical path can easily be found by using a traceback method.
The arrival time of a signal is the time elapsed for a signal to arrive at a certain point. The reference, or time 0.0, is often taken as the arrival time of a clock signal. To calculate the arrival time, delay calculation of all the components in the path will be required. Arrival times, and indeed almost all times in timing analysis, are normally kept as a pair of values—the earliest possible time at which a signal can change, and the latest.
Another useful concept is required time. This is the latest time at which a signal can arrive without making the clock cycle longer than desired. The computation of the required time proceeds as follows: at each primary output, the required times for rise/fall are set according to the specifications provided to the circuit. Next, a backward topological traversal is carried out, processing each gate when the required times at all of its fanouts are known.
The slack associated with each connection is the difference between the required time and the arrival time. A positive slack s at some node implies that the arrival time at that node may be increased by s, without affecting the overall delay of the circuit. Conversely, negative slack implies that a path is too slow, and the path must be sped up (or the reference signal delayed) if the whole circuit is to work at the desired speed.
In static timing analysis, the word static alludes to the fact that this timing analysis is carried out in an input-independent manner, and purports to find the worst-case delay of the circuit over all possible input combinations. During IC operation, electrical signals traverse the IC through the various paths established by the chip designer according to the functions supported by the IC.
The worst-case delay determines the fastest clock speed the IC—or, in some cases, a particular section of a chip—can operate. To ensure that all propagating electrical signals are consistently arriving at their destinations in one clock cycle, the maximum clock frequency that may be used is the one that corresponds to a time period that does not exceed the critical path delay.
The increasing integration scale of modern ICs has led to remarkable increase in the number of paths used to carry and process signals within a chip. EDA tools employ known techniques which help to equalize path delays to some extent, however the design complexity is normally such that some paths inherently have significantly smaller or greater propagation delay than other paths. As such, optimum path equalization is nothing more than a design tradeoff involving chip area constraints, performance (e.g., selecting the highest possible clock frequencies without impacting chip functions), power and/or energy consumption (where the goal may be to reduce clock speed where conservation is a key objective).
As far as chip area constraints, it is known for example to group and pipeline paths by adding gates and other logic to process functions in parallel. While pipelining would normally involve increasing chip area to account for extra registers and other logic circuitry, the fact that certain pipelines may allow an entire clock cycle stage to operate at a higher clock frequency may more than offset, from a design standpoint, any chip size increase.
Conventional integrated circuits and like synchronous digital systems sometimes employ heuristic design algorithms that aim to exploit the slack between the path delays to succeed more efficient implementations. The design complexity to equalize the path delays due to the growing scaling of the IC designs makes the deviations between the path delays a reality.
An asynchronous circuit (or self-timed circuit) differs from a synchronous circuit in that it is a sequential digital logic circuit which is not governed by a clock circuit or global clock signal. Instead, asynchronous circuits use signals that indicate completion of instructions and operations, specified by simple data transfer protocols.
Synchronous design offers low design complexity using a common clock signal, discrete (synchronous) time operation, and a design that may be supported with available automation tools. Asynchronous design, on the other hand, offers performance benefits for large scale integrated circuits with great path delay variability. One disadvantage of synchronous design is the fact that clock frequency is necessarily dependent on critical path delay. In the case of asynchronous design, disadvantages include high design complexity, non-discrete time (asynchronous) operation, and lack of automated tools to support the design.
There is a need to operate synchronous digital systems in yet more optimized manner and address the challenges imposed by critical path delay limitations.